The present invention relates in general to reducing switching losses for power switching devices in DC inverters wherein the devices have enhanced common source inductance, and, more specifically, to provide separate gate drive signals for paralleled power switching devices for selectably switching a selected number of the devices under hard-switching conditions as determined by a magnitude of phase current in order to optimize aggregate switching losses.
Electrified vehicles, such as hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), and battery electric vehicles (BEVs), use inverter-driven electric machines to provide traction torque. A typical electric drive system includes a DC power source (such as a battery pack or a fuel cell) coupled by contactor switches to a variable voltage converter (VVC) to regulate a main bus voltage across a main DC link capacitor. An inverter is connected between the main buses for the DC link and a traction motor in order to convert the DC power to an AC power that is coupled to the windings of the motor to propel the vehicle. A generator inverter may also be connected to the DC link so that AC power from a generator driven by an internal combustion engine can supply DC power onto the link for recharging the battery and/or powering the traction motor.
The inverter(s) and VVC include transistor switching devices (such as insulated gate bipolar transistors, or IGBTs) connected in a bridge configuration including one or more phase legs. A typical configuration includes a three-phase motor driven by an inverter with three phase legs. An electronic controller turns the switches on and off in order to invert a DC voltage from the bus to an AC voltage applied to the motor. The inverter is controlled in response to various sensed conditions including the rotational position of the electric machine and the current flow in each of the phases.
The inverter for the motor may preferably pulse-width modulate the DC link voltage in order to deliver an approximation of a sinusoidal current output to drive the motor at a desired speed and torque. Pulse Width Modulation (PWM) control signals are applied to drive the gates of the IGBTs in order to turn them on and off as necessary. In an idealized form, the gate drive control signals are square wave signals that alternate each power switching device (e.g., IGBT) between a fully off and a fully on (saturated) state. During turn off and turn on, it takes time for the device to respond to the change in the gate drive signal. For example, after the gate drive signal transitions from a turn-off state to a turn-on state, conduction through the device output transitions from zero current flow to a maximum current flow within a few microseconds.
Common source inductance refers to an inductance shared by the main power loop (i.e., the drain-to-source or collector-to-emitter power output of the transistor) and the gate driver loop (i.e., gate-to-source or gate-to-emitter) in a power switching transistor. The common source inductance carries both the device output current (e.g., drain to source current) and the gate charging/discharging current. A current in the output (power loop) portion of the common source inductance modifies the gate voltage in a manner that reinforces (e.g., speeds up) the switching performance. For a switching bridge, the reduced switching time may be desirable since it may have an associated reduction in the energy consumed (i.e., lost) during the switching transition. The magnitude of the gate loop inductance and/or the power loop inductance and the degree of mutual coupling between them can be easily manipulated (e.g., enhanced) by selecting an appropriate layout and/or including added overlapping coils in PCB traces forming conductive paths to the transistor gates or emitters in order to obtain a desired common source inductance.
Since the current-carrying capacity of a power transistor such as an IGBT may be less than a desired maximum load current, inverters for electrified vehicles may often use a plurality of paralleled transistors for the upper and/or lower portions of each phase leg to increase the current handling capability. Typically, the paralleled transistors would be substantially identical (e.g., the same IGBT). The paralleled transistors may all be controlled by the same gate drive signal so that they all turn on and off simultaneously. Alternatively, the transistors can be switched in succession as disclosed in U.S. Pat. No. 8,766,702 wherein two parallel transistors with different characteristics (e.g., different saturation voltages and fall times) are switched in an order that adjusts the switching transients in a manner that results in reduced switching loss.
When the paralleled transistors utilize common source inductance enhancement, switching loss can be reduced without the need for using non-identical transistors. Since the transistors are connected in parallel, the enhanced common source inductances at the individual transistors add together to produce a combined common source inductance that impacts the switching transients. Therefore, the magnitude of the enhancements are designed to optimize switching performance with all transistors being switched while carrying the peak current magnitude. When operating the inverter at lower load currents, the reduction in switching loss can drop significantly because the gate driver starts to lose control of the transistors and the switching behavior becomes dominated by the device characteristics of the transistors instead of by the common source inductance. It would be desirable to maintain the reduction in switching loss over a broad range of load currents.